The present invention generally relates to integrated circuits, and, more particularly, to an integrated circuit with an asynchronous first-in-first-out (FIFO) buffer.
Integrated circuits (ICs) including system-on-chips (SoCs) integrate various digital as well as analog components on a single chip. The ICs communicate with different types of external components including dynamic random access memories (DRAMs), double-data rate (DDR) memories, and Ethernet and universal serial data-bus (USB) devices. For example, a processor of the IC may fetch video data from a DDR memory and display the video data on a display unit coupled to the IC.
Generally, the external components and the IC operate on disparate clock signals, where the IC operates in an asynchronous clock domain with respect to the external components. To facilitate communication between various components, such as the processor and the external components, an asynchronous data transfer system is used. The asynchronous data transfer system includes an asynchronous first-in-first-out (FIFO) buffer and a bus interface unit (BIU). The asynchronous data transfer system is connected to the external components for receiving data from the external components and transferring the received data to the IC via the FIFO buffer.
FIG. 1 is a schematic block diagram of a conventional asynchronous data transfer system 100. The asynchronous data transfer system 100 is used for transferring input data to an asynchronous clock domain. The asynchronous data transfer system 100 is connected to an IC 102 and a DDR memory 104 via a system bus 106.
The IC 102 includes a processor 108 that initiates fetching of the input data from the DDR memory 104. The processor 108 operates based on a read clock (RCLK) signal. To fetch the input data, the processor 108 generates a read increment signal. For example, the processor 108 may fetch the input data from the DDR memory 104 and display the input data on a display unit (not shown) connected to the IC 102.
The asynchronous data transfer system 100 includes a BIU 110, an asynchronous FIFO buffer 112, a FIFO write logic module 114, a write pointer synchronizer 116, a FIFO read logic module 118, and a read pointer synchronizer 120. The BIU 110, the asynchronous FIFO buffer 112, the FIFO write logic module 114, and the read pointer synchronizer 120 operate based on a write clock (WCLK) signal, and hence form a write-clock domain. The FIFO read logic module 118 and the write pointer synchronizer 116 operate based on the read clock (RCLK) signal, and hence, form a read-clock domain.
The BIU 110 is connected to the DDR memory 104 for receiving the input data via the system bus 106. The BIU 110 generates a write increment signal when a fixed amount of the input data is accumulated at the BIU 110, and provides the write increment signal to the FIFO write logic module 114. Subsequently, the BIU 110 provides the input data to the asynchronous FIFO buffer 112.
The FIFO write logic module 114 is connected to the BIU 110 and includes a write counter (not shown) that stores a write address count value indicative of a write address in the asynchronous FIFO buffer 112, which stores the input data. The FIFO write logic module 114 receives the write increment signal and increments the write address count. In one example, if the amount input data accumulated at the BIU 110 is 8 bytes, the write address count is incremented by one. Thus, the incremented write address count refers to a fill level of 8 bytes, i.e., the FIFO buffer 112 is filled with 8 bytes of data. Based on the incremented write address count value, the FIFO write logic module 114 generates and provides a write address signal to the FIFO buffer 112 to initiate storing of the input data. The FIFO buffer 112 receives the input data from the BIU 110 and stores the input data based on the write address signal. After storing the input data at the address of the FIFO buffer 112 indicated by the write address signal, the FIFO write logic module 114 generates a write pointer indicative of the incremented write address count value. The FIFO write logic module 114 provides the write pointer to the write pointer synchronizer 116.
The write pointer synchronizer 116 receives the write pointer and transfers the write pointer from the write-clock domain to the read-clock domain. Thus, the write pointer synchronizer 116 synchronizes the write pointer for the read-clock domain. The write pointer synchronizer 116 may include multiple flip-flops (not shown) that operate using the read clock (RCLK) signal.
The FIFO read logic module 118 is connected to the write pointer synchronizer 116 for receiving the synchronized write pointer. The FIFO read logic module 118 includes a read counter (not shown) that stores a read address count value that is indicative of a read address of the FIFO buffer 112. The read address corresponds to an address of the FIFO buffer 112 that stores the first byte of the input data. The FIFO read logic module 118 is further connected to the processor 108 for receiving the read increment signal and incrementing the read address count. Based on the incremented read address count, the FIFO read logic module 118 generates and provides a read address signal to the FIFO buffer 112 to initiate the transfer of the input data to the processor 108. The FIFO read logic module 118 increments the read address count based on the synchronized write pointer. In one example, if the size of the input data is 8 bytes, the FIFO read logic module 118 increments the read address count by one. The FIFO read logic module 118 further generates a read pointer based on the incremented read address count value. Similarly, the FIFO read logic module 118 transfers the read pointer to the write-clock domain via the read pointer synchronizer 120. The read pointer synchronizer 120 is structurally and functionally similar to the write pointer synchronizer 116.
Thus, the FIFO write logic module 114 uses the write pointer to transfer the input data to the asynchronous clock domain, i.e., the read-clock domain. Conventionally, the FIFO write logic module 114 uses a binary gray code encoder to generate the write pointer based on the write address count value.
FIG. 2 is a schematic block diagram of a conventional binary gray code encoder 202 of the asynchronous data transfer system 100. The FIFO write logic module 114 includes the binary gray code encoder 202. In one example, the binary gray code encoder 202 is a look-up table (LUT) that stores a mapping between multiple write address count values and corresponding write pointers. Each write pointer is an N-bit word that conforms to a binary gray code. Similarly, the FIFO read logic module 118 includes another binary gray code encoder (not shown) for the read address count values. Consecutive binary gray code values differ by 1 bit, and hence, consecutive write pointers also differ by 1 bit. Thus, if a write pointer is transmitted erroneously, the incorrect write pointer will differ by 1 bit. The aforementioned property of the binary gray code allows prevention of a read miss on the FIFO buffer 112 due to erroneously transmitted write pointers, and hence, binary gray codes are used for transmitting read and write pointers across asynchronous clock domains. However, the aforementioned property is true only if the write address count is incremented by a fixed value, i.e., one.
For example, the binary gray code encoder 202 may generate a first data word (000), a second data word (001) and a third data word (011) for first, second and third write address count values, respectively. The write address count value is initially set to the first write address count value. When the BIU 110 accumulates the input data of size 8 bytes, the FIFO write logic module 114 increments the write address count by one, and hence, the incremented write address count value corresponds to the second write address count value. Subsequently, the binary gray code encoder 202 generates the second data word (001) as the write pointer.
If the write pointer synchronizer 116 erroneously transmits the write pointer to the asynchronous clock domain (the read-clock domain), i.e., the least significant bit (LSB) of the second data word fails to toggle, the incorrectly synchronized write pointer either will correspond to either the first data word (000) or the third data word (011). However, since the write address count value is incremented sequentially, the FIFO read logic module 118 determines the incorrectly synchronized write pointer as the first data word (000). Thus, the FIFO read logic module 118 receives a data word corresponding to the previous write address count, and hence, determines that the input data is not stored in the asynchronous FIFO buffer 112. Thus, the FIFO read logic module 118 does not initiate the transfer of the input data to the processor 108.
When the write pointer synchronizer 116 synchronizes the write pointer to the read-clock domain correctly, i.e., the least significant bit (LSB) of the second data word toggles, the synchronized write pointer corresponds to the second data word (001). The FIFO read logic module 118 determines that the input data of 8 bytes is stored in the FIFO buffer 112, and hence, initiates the transfer of the input data to the processor 108. Thus, due to the use of binary gray code, the error in the synchronized write pointer does not lead to a read miss of the FIFO buffer 112 at the read-clock domain.
However, to retain the aforementioned property for preventing a read miss of the FIFO buffer 112, the write address count must be incremented sequentially and by a fixed value for a fixed size of input data. In one example, if the BIU 110 writes input data of size 16 bytes, the FIFO write logic module 114 increments the write address count by 2, and hence, the incremented write address count corresponds to the third write address count value. Subsequently, the binary gray code encoder 202 generates the third data word (011) as the write pointer.
Thus, the incorrectly synchronized write pointer may refer to either the second data word (001) or the fourth data word (010). Since the write address count is always incremented by one, the FIFO read logic module 118 may determine the incorrect synchronized write pointer as the fourth data word (010). As a result, the FIFO read logic module 118 determines a fill level of 24 bytes instead of 16 bytes, and hence, the processor 108 encounters a read miss of the FIFO buffer 112 for the penultimate 8 bytes. Therefore, the processor 108 generates a transmission error, and hence, may halt subsequent processing of the input data. Thus, the write address count is always incremented sequentially at fixed size intervals. Conventionally, the FIFO write logic module 114 increments the write address count every 8 bytes of input data stored in the FIFO buffer 112. To enable writing a fixed size of input data to the FIFO buffer 112, the BIU 110 includes an accumulator (not shown) for accumulating the input data received from the system bus 106 until a fill level of 8 bytes is reached. In one example, the accumulator is a cache memory. When the BIU 110 accumulates 8 bytes of input data, the BIU 110 generates the write increment signal to initiate writing of the input data to the FIFO buffer 112.
FIG. 3 is a timing diagram illustrating the transfer of input data across asynchronous clock domains of the asynchronous data transfer system 100. From T0-T2, the system bus 106 receives and outputs input data of size 2 bytes to the BIU 110. From T1-T3, the BIU 110 receives the input data of size 2 bytes and accumulates 2 bytes of data. From T2-T4, the system bus 106 receives and outputs input data of size 4 bytes to the BIU 110. From T3-T5, the BIU 110 receives the input data of size 4 bytes, and hence, accumulates 6 bytes. From T4-T7, the system bus 106 receives and outputs input data of size 6 bytes to the BIU 110. From T5-T7, the BIU 110 receives the input data of size 6 bytes, and hence, accumulates 12 bytes. Since the fill level of the accumulator, which is 8 bytes, is exceeded, at T7 the BIU 110 generates the write increment signal. Thus, at T7, the FIFO write logic module 114 initiates storing of 8 bytes of the accumulated input data in the FIFO buffer 112.
Due to the constraint of writing a fixed amount (size) of input data to the FIFO buffer 112, the input data received at T0 is written to the FIFO buffer 112 at T7. Thus, a delay is introduced in the asynchronous data transfer system 100. The aforementioned delay sacrifices bandwidth across the FIFO buffer 112, and hence, results in latencies in the operation of the processor 108 and the IC 102. Thus, the asynchronous data transfer system 100, which uses the binary gray code encoder 202, is not suitable for low latency and high bandwidth application-based ICs. Further, ICs that are used for applications such as display, unpack pixel components that are in alpha red blue green (ARGB) and YUV formats by accessing unaligned data from the double-data rate (DDR) memory. Therefore, such application-based ICs require transfer of input data of variable size across the asynchronous clock domains. Thus, the asynchronous data transfer system 100 that uses the binary gray code encoder 202 is not suitable for such application-based ICs.
One known asynchronous data transfer system that overcomes the aforementioned problems and enables transmission of variable size input data across asynchronous clock domains includes a main FIFO buffer for transferring input data of variable size and multiple auxiliary FIFO buffers for transferring read and write pointers, respectively, across asynchronous clock domains. However, this technique requires additional auxiliary FIFO buffers and additional logic modules associated therewith, and hence, results in an increase in the area and complexity of the data transfer circuitry. Thus, there is need for an asynchronous data transfer system that accommodates transmission of input data having variable size across asynchronous clock domains without increasing the area and complexity of the asynchronous data transfer system.